1. Field of the Invention
The present invention relates to the design of memories, and more specifically to a sense amplifier which senses the output received from a bit cell of a memory array as either 0 or 1.
2. Related Art
A memory array generally contains multiple cells, with each cell storing a data bit (typically of binary value). Memory arrays are implemented using technologies such as SRAMs (static random access memories) and DRAM (dynamic RAMs), as is well known in the relevant arts.
A sense amplifier is often provided associated with such memory arrays. A sense amplifier generally determines whether a signal received on a bit line represents a 0 or 1. The signal in turn is propagated/presented on the bit line based on a specific cell selected (usually based on a memory address) in the memory array. Thus, the sense amplifier generally provides an output indicating whether the bit in the selected cell represents a 0 or 1.
In general, the combination of memory arrays and sense amplifier need to be designed meeting several requirements. Examples of such requirements include one or more of minimizing electrical power consumption, minimizing total space consumed, high access rates, decreasing circuit complexity, accurate operation over a wide range of process-temperature-voltage combinations.
In one prior embodiment, an inverter is provided at the end of a bit line, and the selected bit cell needs to be generally designed to apply sufficient voltage strength to the bit line to drive the inverter from one logical value to another logical value if the selected bit cell stores a specific bit value (e.g., 1).
One problem with such an approach is that the memory access rates of corresponding implementations are generally low since the voltage level required to drive the inverter from one logical value to another is generally high. The access rates may be improved by using bit cells of high drive strength, which generally implies that the bit cells need to be implemented to be of large size. Large sized bit cells usually means that the memory arrays would be low density (i.e., consume more space) and/or consume more electric power.
Some of such disadvantages are overcome in an alternative prior embodiment by providing a reference signal, which is compared with the signal strength (e.g., voltage level) on a bit line (driven by a selected bit cell when being accessed). The reference signal is chosen to be of adequately high level such that the actual bit value can be reliably distinguished, and is low enough such that the memory cells can be implemented with a low drive strength.
One problem with such an approach is that generating the reference signal accurately may pose challenges in design/implementation of the corresponding solutions. In addition, the reference signal may need to be high enough causing a correspondingly high amount of electrical power to be consumed.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.